ESD (electrostatic discharge) and EOS (electric overstress) protection design is a major factor in the reliability of deep-submicron CMOS Integrated Circuits (IC's ). Since CMOS development technology is aggressive in the deep-submicron category, the device size and the thickness of the gate oxide are being continually reduced to improve the operating speed of the CMOS devices and integration density of the IC's. These highly scaled-down devices, however, have been found to be increasingly vulnerable to ESD and EOS. Therefore, ESD/EOS protection circuits have been added into the CMOS IC's to protect the IC's against ESD/EOS damage. Typically, ESD/EOS protection circuits are implemented around the input and output pads of the IC's to bypass ESD/EOS current away from the internal circuits of the IC's.
As a result of detailed investigations of ESD/EOS events on IC products, it is known that there are three main types of ESD/EOS events: Human-Body Model (HBM), Machine Model (MM), and Charged-Device Model (CDM).
The equivalent circuits of these three ESD models are illustrated in FIG. 1. In the HBM and MM models, FIG. 1(a) and (b), respectively, the discharge current of the ESD/EOS event is from the outside of the IC into the inside of the IC, through the input or output pins. Therefore, the ESD protection circuit is designed to limit the ESD current into the internal parts of the IC from the input or output pins.
A typical design for an ESD protection circuit 10 for HBM and MM ESD events is shown in FIG. 2, where there are primary and secondary ESD protection elements 40, 30, respectively. When an HBM or MM ESD voltage V.sub.ESD appears at the input pad 20, it acts as an input signal to the gate oxide 25 of the input stage. Since this ESD voltage V.sub.ESD may be sufficient to damage the gate oxide 25 of the input stage, it must be clamped by the ESD protection elements 40, 30. In FIG. 2, a short-channel thin-oxide NMOS is used as the secondary protection element 30 to first limit the ESD voltage V.sub.ESD across the gate oxide of the input stage. The short-channel thin-oxide NMOS 30 is designed to operate in its snapback-breakdown region, in order to clamp the voltage level across the gate oxide 25 of the input stage at as low a level as possible, when V.sub.ESD is positive.
A shorter channel length of the NMOS provides a lower snapback-breakdown voltage for clamping an ESD voltage, but is only effective at low ESD levels. Therefore, a primary ESD protection element 40, with greater ESD robustness is typically also connected to the input pad 20 to provide the main bypass for the ESD current. The devices commonly used as primary ESD protection elements are long-channel NMOS, field-oxide device (lateral bipolar transistor), or lateral SCR devices. The primary ESD protection devices with high ESD protection levels generally have a relatively high trigger (or breakdown) voltage, so that the secondary ESD protection device is activated first to clamp the ESD voltage across the gate oxide. Then, due to the increase of voltage drop across the series resistor R and the broken-down secondary ESD protection device 30, the primary ESD protection element 40 is triggered to bypass the main ESD current. Suitable designs of the ESD protection circuit of FIG. 2 can provide the input pads of IC's with high ESD robustness against HBM and MM ESD events.
In the CDM ESD model, as shown in FIG. 1(c), the ESD voltage V.sub.ESD does not come from outside the IC 15, but rather from the device itself. The substrate of the IC 15 is assumed to be charged in a CDM ESD event, and then a pin 5 of the IC 15 is shorted to ground. The charging process does not subject the IC to any ESD damage. The static charge is stored in the equivalent capacitance (Cd) of the IC 15, which is dependent on the chip size and the type of IC package. The equivalent resistance (Rd) and inductance (Ld) of the IC 15 are also dependent on the IC itself and its package. When pin 5 of the charged IC touches ground, the discharge (ESD) current goes from the charged IC 15 to ground through pin 5. This CDM ESD current is discharged from the inside of the IC 15 to the outside of the IC 15. The discharging mechanism of the CDM ESD event is, therefore, quite different from that of the HBM or MM ESD events, and results in different kinds of ESD damage to the IC.
A typical design for an ESD/EOS protection circuit 10 for a CDM ESD/EOS events is shown in FIG. 3, where there are primary and secondary ESD/EOS protection elements 34, 36, respectively. Specifically, a signal is applied at an input pad or pin 32. A first transistor 31 and a second transistor 33 comprise the primary ESD/EOS protection circuit 34, and are employed to discharge high voltage pulses. A negative-going pulse generated by an ESD/EOS event is discharged via first transistor 31. The gate of the first transistor is tied to Vcc. The negative-going ESD/EOS pulse will turn off the second transistor 33, which has a source connected to ground Vss. Typically, the primary circuit 34 discharges most of the ESD/EOS pulses by establishing a path to either Vcc or Vss. The second ESD/EOS protection circuit 36, is designed to the discharge the remainder of the charge by means of drain voltage punch-through. In addition, resister 36 is included between input pad 32 and the internal circuitry 35 to ensure that the first and second transistors 31 and 33 are the lower impedance paths for discharging most of the charge from an ESD/EOS event before reaching the thin gate of the second ESD/EOS protection circuit 36.
However, the thin gate transistor of circuit 36 is susceptible to gate aided junction breakdown. If the voltage across the transistor exceeds the breakdown voltage of the device, damage to the transistor may result in permanent shorting of the input signal to ground Vss.
In addition, during an ESD/EOS event, especially in a PS mode (where ESD/EOS stress is a positive ESD/EOS voltage relative to a grounded Vss pin), the voltage at node B will be at the clamping voltage. We may assume that the primary circuit 34 of FIG. 3 is NMOS. Therefore, at a 0.5 .mu.m process, the NMOS breakdown voltage is approximately 12 V, and the gate oxide thickness at breakdown is approximately 90 to 120 .ANG.. Under such conditions, the input buffer 35 is susceptible to the gate-oxide breakdown failure during an ESD/EOS event.
Accordingly, it is an object of the present invention to overcome the deficiencies in the prior art.